The invention relates generally to a semiconductor device and, more particularly, to an isolation structure in a memory device and a method for fabricating the isolation structure.
Circuit patterns of highly integrated semiconductor memory devices are formed according to small design rules. For example, circuit patterns of dynamic random access memory (DRAM) devices are finely formed according to design rules of approximately 50 nm or less. Since semiconductor memory devices are fabricated according to small design rules, improved gap filling methods are required to form isolation structures in the semiconductor memory devices. For example, when a shallow trench isolation (STI) method is used for forming isolation structures in a highly integrated semiconductor memory device, the use of a dielectric material having good gap-filling characteristics is important since trenches having narrow widths and large aspect ratios are used in the STI method.
When 50 nm or smaller design rules are used, it is difficult to fill a trench through a high density plasma (HDP) process. To address this difficulty, flowable dielectric materials having better gap-filling characteristics than HDP oxides can be used to fill trenches. In detail, a liquid or suspension of a dielectric material source is useful to fill trenches owing to the good fluidity of such liquids and suspensions. Then, the applied liquid or suspension is cured to form an isolation dielectric layer in the trenches. For example, the liquid or suspension can be applied using a spin coater. In this case, a spin on dielectric (SOD) layer may be formed as the isolation dielectric layer.
However, when flowable dielectrics are used to fill trenches, undesired punchthrough can be observed in a p-channel metal oxide semiconductor (PMOS) transistor. For example, undesired hot electron induced punchthrough (HEIP) can occur in PMOS transistors, which are generally formed in a peripheral region of a DRAM device. It is considered that the punchthrough phenomenon is caused by a nitride liner layer disposed between a flowable dielectric layer and walls of a trench.
FIGS. 1 and 2 illustrate schematic views for explaining HEIP of a PMOS transistor.
Referring to FIGS. 1 and 2, an isolation layer 20 can be formed into an STI structure so as to define an active region 10 in a semiconductor substrate. In this case, operations of a gate 30 of a PMOS transistor formed in the active region 10 are affected by an effective channel width of the active region 10. The effective channel width of the active region 10 is determined by the width of the active region 10 and charge distribution along the interface between the active region 10 and the isolation layer 20.
For example, in a DRAM device having a small design rule, many hot electrons are generated due to strong electric fields between channels. Such hot electrons (indicated by “e” in FIG. 1) permeate the isolation layer 20 and are trapped in the isolation layer 20 in the vicinity of the interface between the active region 10 and the isolation layer 20. The trapped hot electrons (e) attract p-type carriers (i.e., holes (+)) such that the p-type carriers are trapped in a portion of the active region 10 close to the isolation layer 20. The trapped p-type carriers may reduce the effective channel width of the PMOS transistor. In this case, the threshold voltage of the PMOS transistor is greatly reduced. Therefore, off leakage current of the PMOS transistor may increase significantly when the PMOS transistor is turned off.
Referring to FIG. 2, a three-layer liner is disposed between the active region 10 and the isolation layer 20 for improving interface characteristics between the active region 10 and the isolation layer 20. The three-layer liner includes a first silicon oxide layer 21, a silicon nitride layer 23, and a second silicon oxide layer 25. Owing to a potential well of the three-layer liner, hot electrons (e) can be trapped in the silicon nitride layer 23. Significantly, such hot electrons (e) trapped in trap sites of the silicon nitride layer 23 deteriorate HEIP characteristics of the PMOS transistor.
If the isolation layer 20 is formed of a flowable dielectric layer, the HEIP characteristics of the PMOS transistor may be more greatly deteriorated. In detail, while a flowable liquid dielectric material source is applied and cured to form the isolation layer 20, the isolation layer 20 and the silicon nitride layer 23 can be subjected to mechanical stress. For example, when the flowable liquid dielectric material source is cured to form the isolation layer 20, the isolation layer 20 and the silicon nitride layer 23 can be subjected to mechanical stress due to shrinkage of the flowable liquid dielectric material source. Such stresses increase electron trap sites of the silicon nitride layer 23, and thus more electrons can be trapped in the silicon nitride layer 23. This results in the same effect as the case where electrons are trapped in a portion of the isolation layer 20 close to the active region 10 as shown in FIG. 1. Therefore, the HEIP characteristics of the PMOS transistor deteriorate more significantly.